IRFR9010, irfu9010, sihfr9010, sihfu9010 www.vishay.com vishay siliconix s13-0167-rev. d, 04-feb-13 1 document number: 91378 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power mosfet features ? surface mountable (order as IRFR9010, sihfr9010) ? straight lead option (order as irfu9010, sihfu9010) ? repetitive avalanche ratings ? dynamic dv/dt rating ? simple drive requirements ? ease of paralleling ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 description the power mosfet technology is the key to vishays advanced line of power mosfet transistors. the efficient geometry and unique processing of this latest state of the art design achieves: very low on-state resistance combined with high transcon ductance; superior reverse energy and diode recovery dv/dt capability. the power mosfet transistors also feature all of the well established advantages of mosfets such as voltage control, very fast switching, ease of paralleling and temperature stability of th e electrical parameters. surface mount packages enha nce circuit performance by reducing stray inductances and capacitance. the dpak (to-252) surface mount package brings the advantages of power mosfets to high volume applications where pc board surface mounting is de sirable. the surface mount option IRFR9010, sihfr9010 is provided on 16 mm tape. the straight lead option irfu9010, sihfu9010 of the device is called the ipak (to-251). they are well suited for applications where limited heat dissipation is required such as, computers and peripherals, telecommunication equipment, dc/dc converters, and a wide range of consumer products. note a. see device orientation. notes a. repetitive rating; pu lse width limited by maximum junction temperature (see fig. 14). b. v dd = - 25 v, starting t j = 25 c, l = 9.7 mh, r g = 25 ? , peak i l = - 5.3 a. c. i sd ? - 5.3 a, di/dt ? - 80 a/s, v dd ? 40 v, t j ? 150 c, suggested r g = 24 ? . d. 0.063" (1.6 mm) from case. product summary v ds (v) - 50 r ds(on) ( ? )v gs = - 10 v 0.50 q g (max.) (nc) 9.1 q gs (nc) 3.0 q gd (nc) 5.9 configuration single s g d p-channel mosfet dpak (to-252) ipak (to-251) g d s s d g d ordering information package dpak (to-252) dpak (to- 252) dpak (to-252) ipak (to-251) lead (pb)-free and halogen- free sihfr9010-ge3 sihfr9010tr-ge3 a sihfr9010trl-ge3 a sihfu9010-ge3 lead (pb)-free IRFR9010pbf IRFR9010trpbf a IRFR9010trlpbf a irfu9010pbf sihfr9010-e3 sihfr9010t-e3 a sihfr9010tl-e3 a sihfu9010-e3 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds - 50 v gate-source voltage v gs 20 continuous drain current v gs at - 10 v t c = 25 c i d - 5.3 a t c = 100 c - 3.3 pulsed drain current a i dm - 21 linear dera ting factor 0.20 w/c single pulse avalanche energy b e as 136 mj repetitive avalanche current a i ar - 5.3 a repetitive avalanche energy a e ar 2.5 mj maximum power dissipation t c = 25 c p d 25 w peak diode recovery dv/dt c dv/dt 5.8 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (peak temperature) d for 10 s 300
IRFR9010, irfu9010, sihfr9010, sihfu9010 www.vishay.com vishay siliconix s13-0167-rev. d, 04-feb-13 2 document number: 91378 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note a. mounting pad must cover heatsink surface area. notes a. repetitive rating; pu lse width limited by maximum junction temperature (see fig. 14). b. pulse width ? 300 s; duty cycle ? 2 %. thermal resistance ratings parameter symbol min. typ. max. unit maximum junction-to-ambient r thja - - 110 c/w case-to-sink r thcs -1.7- maximum junction-to-case (drain) a r thjc --5.0 specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 50 - - v gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 2.0 - - 4.0 v gate-source leakage i gss v gs = 20 v - - 500 na zero gate voltage drain current i dss v ds = max. rating, v gs = 0 v - - - 250 a v ds = 0.8 x max. rating, v gs = 0 v, t j = 125 c - - - 1000 drain-source on-state resistance r ds(on) v gs = - 10 v i d = - 2.8 a b - 0.35 0.5 ? forward transconductance g fs v ds ? - 50 v, i ds = - 2.8 a 1.1 1.7 - s dynamic input capacitance c iss v gs = 0 v, v ds = - 25 v, f = 1.0 mhz, see fig. 9 -240- pf output capacitance c oss -160- reverse transfer capacitance c rss -30- total gate charge q g v gs = - 10 v i d = - 4.7 a, v ds = 0.8 x max. rating, see fig. 16 (independent operating temperature) -6.19.1 nc gate-source charge q gs -2.03.0 gate-drain charge q gd -3.95.9 turn-on delay time t d(on) v dd = - 25 v, i d = - 4.7 a, r g = 24 ? , r d = 5.6 ? , see fig. 15 (independent operating temperature) -6.19.2 ns rise time t r -4771 turn-off delay time t d(off) -1320 fall time t f -3559 internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact. -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-dra in diode current i s mosfet symbol showing the integral reverse p - n junction diode --- 5.3 a pulsed diode forward current a i sm --- 18 body diode voltage v sd t j = 25 c, i s = - 5.3 a, v gs = 0 v b --- 5.5v body diode reverse recovery time t rr t j = 25 c, i f = - 4,7 a, di/dt = 100 a/s b 33 75 160 ns body diode reverse recovery charge q rr 0.090 0.22 0.52 c forward turn-on time t on intrinsic turn-on time is negligib le (turn-on is dominated by l s and l d ) d s g s d g
IRFR9010, irfu9010, sihfr9010, sihfu9010 www.vishay.com vishay siliconix s13-0167-rev. d, 04-feb-13 3 document number: 91378 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical transfer characteristics fig. 3 - typical saturation characteristics fig. 4 - maximum safe operating area fig. 5 - typical transconductance vs. drain current fig. 6 - typical source-drain diode forward voltage
IRFR9010, irfu9010, sihfr9010, sihfu9010 www.vishay.com vishay siliconix s13-0167-rev. d, 04-feb-13 4 document number: 91378 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 7 - breakdown voltage vs. temperature fig. 8 - normalized on-resistance vs. temperature fig. 9 - typical capacitance vs. drain-to-source voltage fig. 10 - typical gate charge vs. gate-to-source voltage
IRFR9010, irfu9010, sihfr9010, sihfu9010 www.vishay.com vishay siliconix s13-0167-rev. d, 04-feb-13 5 document number: 91378 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 11 - typical on-res istance vs. drain current fig. 12 - maximum drain curre nt vs. case temperature fig. 13a - maximum avalanch e vs. starting junction temperature fig. 13b - unclamped inductive test circuit fig. 13c - unclamped inductive waveforms r g i l 0.05 t p d.u.t. l v ds + - v dd - 10 v var y t p to obtain required i l i as v ds v dd v ds t p i l
IRFR9010, irfu9010, sihfr9010, sihfu9010 www.vishay.com vishay siliconix s13-0167-rev. d, 04-feb-13 6 document number: 91378 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 14 - maximum effective transient thermal impedance, junction-to-case vs. pulse duration fig. 15a - switching time waveforms fig. 15b - switching time test circuit fig. 16a - basic gate charge waveform fig. 16b - gate charge test circuit v gs 10 % 90 % v ds t d(on) t r t d(off) t f pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. - 10 v + - v ds v dd q gs q gd q g v g charge - 10 v d.u.t. - 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
IRFR9010, irfu9010, sihfr9010, sihfu9010 www.vishay.com vishay siliconix s13-0167-rev. d, 04-feb-13 7 document number: 91378 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 17 - for p-channel vishay siliconix maintains worldwide manufactu ring capability. products may be manufact ured at one of seve ral qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91378 . p.w. period di/dt diode recovery dv/dt body diode forward drop body diode forward current driver gate drive inductor current d = p.w. period + - - - - + + + peak dio d e recovery d v/ d t test circuit ? dv/dt controlled by r g ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low stray inductance ? g round plane ? low leakage inductance current tran s former r g ? compliment n-channel of d.u.t. for driver v dd ? i s d controlled by duty factor d note note a. v gs = - 5 v for logic level and - 3 v drive device s v gs = - 10 v a d.u.t. l s d waveform d.u.t. v d s waveform v dd re-applied voltage ripple 5 % i s d rever s e recovery current
package information www.vishay.com vishay siliconix revision: 03-jun-13 1 document number: 71197 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 to-252aa case outline notes ? dimension l3 is for reference only. ? xian, mingxin, and gem sh actual photo. l3 d l4 l5 b b2 e1 e1 d1 c a1 gage plane height (0.5 mm) e b3 e c2 a l h millimeters inches dim. min. max. min. max. a 2.18 2.38 0.086 0.094 a1 - 0.127 - 0.005 b 0.64 0.88 0.025 0.035 b2 0.76 1.14 0.030 0.045 b3 4.95 5.46 0.195 0.215 c 0.46 0.61 0.018 0.024 c2 0.46 0.89 0.018 0.035 d 5.97 6.22 0.235 0.245 d1 4.10 - 0.161 - e 6.35 6.73 0.250 0.265 e1 4.32 - 0.170 - h 9.40 10.41 0.370 0.410 e 2.28 bsc 0.090 bsc e1 4.56 bsc 0.180 bsc l 1.40 1.78 0.055 0.070 l3 0.89 1.27 0.035 0.050 l4 - 1.02 - 0.040 l5 1.01 1.52 0.040 0.060 ecn: t13-0359-rev. o, 03-jun-13 ? dwg: 5347
application note 826 vishay siliconix document number: 72594 www.vishay.com revision: 21-jan-08 3 application note recommended minimum pads for dpak (to-252) 0.420 (10.668) recommended mi nimum pads dimensions in inches/(mm) 0.224 (5.690) 0.180 (4.572) 0.055 (1.397) 0.243 (6.180) 0.087 (2.202) 0.090 (2.286) return to index return to index
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